VHDL 8 位二进制到 BCD 转换器循环语句错误

如何解决VHDL 8 位二进制到 BCD 转换器循环语句错误

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity BCD_converter8 is
    port(X: in std_logic_vector(7 downto 0);
          S: out std_logic_vector(11 downto 0));
end BCD_converter8;

architecture sample of BCD_converter8 is

    signal f1,f2,f3: std_logic_vector(3 downto 0);
    signal n1,n2,n3: integer;
    signal i: integer;
    signal a,b: integer;
    
    begin
    
    a <= conv_integer(X,8);
    
    b <= a / 10;
    n1 <= b / 10;
    n2 <= b rem 10;
    n3 <= a rem 10;
    
    for i in 1 to 3 loop
        case n(i) is
            when '0' => f(i) <= "0000";
            when '1' => f(i) <= "0001";
            when '2' => f(i) <= "0010";
            when '3' => f(i) <= "0011";
            when '4' => f(i) <= "0100";
            when '5' => f(i) <= "0101";
            when '6' => f(i) <= "0110";
            when '7' => f(i) <= "0111";
            when '8' => f(i) <= "1000";
            when '9' => f(i) <= "1001";
            when others => null;
        end case;
    end loop;
    
    S(11 downto 8) <= f1(3 downto 0);
    S(7 downto 4) <= f2(3 downto 0);
    S(3 downto 0) <= f3(3 downto 0);
    
end sample;

以上代码是针对接收8位二进制数并将其转换为BCD码的行为而设计的。首先，将二进制代码转换为整数并除以10，通过余数和商确定它们各自的位数。并且是为每个数字分配一个BCD码。

可以使用 fi 重复 f1,2,3 吗？

并且错误发生在循环和 case 语句中。 这时候继续出现下面的错误语句，但是在loop和case语句中找不到问题。你能告诉我如何解决下面的错误吗？

(10500) 靠近文本“开始”；期待“结束”，“（”，标识符（“开始”是保留关键字）或并发语句

(10500) 靠近文本“when”；期待“结束”，“（”，标识符（“when”是保留关键字）或并发语句