ModelSim：Altera On-Chip Flash 在 readdata 中没有响应

如何解决ModelSim：Altera On-Chip Flash 在 readdata 中没有响应

波形模型：https://i.stack.imgur.com/qpBhr.png

带有 .dat 文件的闪存的 Quartus 初始化： https://i.stack.imgur.com/SXH83.png

模拟器中的altera_onchip_flash_block： https://i.stack.imgur.com/X20kI.png

我似乎无法从我的 Altera On-Chip Flash 中得到响应。我已经用 Quartus 生成了它，并通过 Quartus 用 .dat 文件对其进行了初始化。当我只模拟 IPcore 时，它​​工作正常，但在我必须为我的公司使用的测试平台环境中，我得到未定义的 data_readdata。

如第三个屏幕截图和 ModelSim 的错误消息所示，DIN/drdin 出现问题。

我使用 MAX 10 FPGA 和 VHDL 作为语言。

这就是我在我的 ufm 架构中实例化它的方式。然后我使用状态机读取地址 000 到 005，然后重复。

     component ufmIP is
        port (
            clock                   : in  std_logic                     := 'X';             -- clk
            avmm_csr_addr           : in  std_logic                     := 'X';             -- address
            avmm_csr_read           : in  std_logic                     := 'X';             -- read
            avmm_csr_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            avmm_csr_write          : in  std_logic                     := 'X';             -- write
            avmm_csr_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
            avmm_data_addr          : in  std_logic_vector(11 downto 0) := (others => 'X'); -- address
            avmm_data_read          : in  std_logic                     := 'X';             -- read
            avmm_data_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            avmm_data_write         : in  std_logic                     := 'X';             -- write
            avmm_data_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
            avmm_data_waitrequest   : out std_logic;                                        -- waitrequest
            avmm_data_readdatavalid : out std_logic;                                        -- readdatavalid
            avmm_data_burstcount    : in  std_logic_vector(3 downto 0) := (others => 'X');  -- burstcount
            reset_n                 : in  std_logic                    := 'X'               -- reset_n
        );
    end component ufmIP;

    flash : component ufmIP
        port map (
            clock                   => clock,--    clk.clk
            avmm_csr_addr           => avmm_csr_addr,--    csr.address
            avmm_csr_read           => avmm_csr_read,--       .read
            avmm_csr_writedata      => avmm_csr_writedata,--       .writedata
            avmm_csr_write          => avmm_csr_write,--       .write
            avmm_csr_readdata       => avmm_csr_readdata,--       .readdata
            avmm_data_addr          => avmm_data_addr,--   data.address
            avmm_data_read          => avmm_data_read,--       .read
            avmm_data_writedata     => avmm_data_writedata,--       .writedata
            avmm_data_write         => avmm_data_write,--       .write
            avmm_data_readdata      => avmm_data_readdata,--       .readdata
            avmm_data_waitrequest   => avmm_data_waitrequest,--       .waitrequest
            avmm_data_readdatavalid => avmm_data_readdatavalid,--       .readdatavalid
            avmm_data_burstcount    => avmm_data_burstcount,--       .burstcount
            reset_n                 => reset_n                  -- nreset.reset_n
        );

when read =>
                    avmm_data_read <= '1';
                    -- data addresses as defined
                    case read_from is
                        when crc =>
                            avmm_data_addr <= x"000";
                    ....

ModelSim 显示的消息：

# ufm_testbench.ufm_inst.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 0.01ns: WARNING: SE shows unknown state!
# FLASH_READY detected
# ufm_testbench.ufm_inst.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 525.00ns: WARNING: DIN shows unknown state!
# ** Error: $hold( posedge <protected> &&& <protected>:520100 ps,negedge <protected>:530 ns,26 ns );
#    Time: 530 ns  Iteration: 7  Protected: /ufm_testbench/ufm_inst/flash/onchip_flash_0/altera_onchip_flash_block/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/#Setuphold# File: C:/intelfpga_lite/20.1/quartus/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
# ** Error: $hold( posedge <protected> &&& <protected>:520100 ps,26 ns );
#    Time: 530 ns  Iteration: 7  Protected: /ufm_testbench/ufm_inst/flash/onchip_flash_0/altera_onchip_flash_block/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/#Setuphold# File: C:/intelfpga_lite/20.1/quartus/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
# ufm_testbench.ufm_inst.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 535.00ns: WARNING: DIN shows unknown state!
# ufm_testbench.ufm_inst.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 545.00ns: WARNING: DIN shows unknown state!
# ufm_testbench.ufm_inst.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 555.00ns: WARNING: DIN shows unknown state!
# ufm_testbench.ufm_inst.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 565.00ns: WARNING: DIN shows unknown state!
# 
# TESTBENCH: END OF SIMULATION!!! ```