我不知道在 VHDL testbench 的时间间隔上写什么

如何解决我不知道在 VHDL testbench 的时间间隔上写什么

我正在编写两个 VHDL 代码；一个用于 ALU，另一个用于双端口数据存储器。

在 Stack Overflow 的贡献者提供一些有用的建议之后，我设法为 ALU 和双端口数据存储器提出了以下 VHDL 代码。

问题是，我不知道在内存的测试台上放什么才能真正让所有地址都显示在模拟中，至于 ALU 代码，我不确定模拟结果是否正确。

ALU 测试台的目的是显示 VHDL 代码中规定的所有操作，显示在仿真中，内存测试台的目的是测试所有地址值是否在 VHDL 上实现代码显示在模拟中。有人可以帮忙，因为这对我完成它非常重要。非常感谢决定提供帮助的人。刚开始学VHDL，错误太多请见谅。

这是 ALU 的 VHDL 代码：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alu is
    port (
    A,B: in signed (31 downto 0);
            opcode: in std_logic_vector(5 downto 0);
            Result: out signed (31 downto 0));            
end entity alu;

architecture dataoperations of alu is
begin 
process (A,B,opcode)
begin
    Result <= A + B when opcode="001010" -- Addition
    else    A - B when opcode="001000" --Subtraction
    else    abs(A) when opcode="001011" --Absolute value of A
    else    -A  when opcode="001101" --Minus A
    else    abs(B) when opcode="000001" -- Absolute value of B
    else    -B when opcode="001001" --Minus B
    else    A or B when opcode="000110" --A or B
    else    not A when opcode="001111" --Not A 
    else    not B when opcode="000101" --Not B
    else    A and B when opcode="001100" -- A and B
    else    A xor B when opcode="000010"; --A exclusive or B

end process;

end architecture dataoperations;

这是 ALU 的测试平台：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alu_test is
end entity alu_test;

architecture test of alu_test is

-- Introducing the Unit Under Test (UUT),in this case,the ALU

component alu
port ( A,B: in signed (31 downto 0) := (others => '0');
            opcode: in std_logic_vector(5 downto 0) := (others => '0');
            Result: out signed (31 downto 0));
end component;            
    
    -- Input generator
    signal A,B: signed (31 downto 0) := (others => '0');
    signal opcode: std_logic_vector (5 downto 0) := (others => '0') ;
    -- Output display
    signal Result: signed (31 downto 0);
    
begin
    
    uut:alu
        port map ( A => A,B => B,opcode => opcode,Result => Result );
   
    stimulus_process: process 
    begin
    
    wait for 5 ns;
    
    
    A <= "00000000000000000000000000001001";
    B <= "00000000000000000000000000001111";
    
    opcode <= "001010";
    wait for 5 ns;
    opcode <= "001000";
    wait for 5 ns;
    opcode <= "001011";
    wait for 5 ns;
    opcode <= "001101";
    wait for 5 ns;
    opcode <= "000001";
    wait for 5 ns;
    opcode <= "001001";
    wait for 5 ns;
    opcode <= "000110";
    wait for 5 ns;
    opcode <= "001111";
    wait for 5 ns;
    opcode <= "000101";
    wait for 5 ns;
    opcode <= "001100";
    wait for 5 ns;
    opcode <= "000010";
    end process;
   
end;

数据存储器的 VHDL 代码：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; 
entity rom is
    port ( addr1,addr2: in unsigned (4 downto 0);
      data_out1,data_out2: out unsigned (31 downto 0));
end entity rom;

architecture dataflow of rom is
    type rom_array is array (0 to 31) 
                    of std_logic_vector (31 downto 0);
    signal rom_data: rom_array := 
                    (x"00000000",x"00000000",x"000005E4",x"0000EE7C",x"000175FE",x"00000BAE",x"0000E4E0",x"00000F20",x"00013CE3",x"000072B0",x"000075BE",x"00005974",x"0000DC71",x"00009064",x"0000D246",x"00017CE1",x"00015275",x"00011CD8",x"000131F3",x"00013B3F",x"00000149",x"000124D5",x"000051CD",x"00015A16",x"00016EAE",x"0000A312",x"00007F96",x"000161A4",x"0001673C",x"00005E6F",x"000154B5",x"00000000");


end architecture dataflow;

还有测试平台：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity rom_test is
end entity rom_test;

architecture behavIoUr of rom_test is

-- Introducing the UUT,here it is rom

component rom
port ( addr1,data_out2: out unsigned (31 downto 0));
end component;

    signal addr1,addr2: unsigned (4 downto 0);
    signal data_out1,data_out2: unsigned (31 downto 0);
    
begin

    uut: rom
        port map ( addr1 => addr1,addr2 => addr2,data_out1 => data_out1,data_out2 => data_out2 );

此外，它是一个具有 6 位操作码的 32 位 ALU，它是一个具有 5 位输入（在每个端口上）和 32 位输出的双端口数据存储器。