VHDL 和或反相电路，在仿真期间的前 5 ns 内输出未确定内部信号也没有显示在波形上

如何解决VHDL 和或反相电路，在仿真期间的前 5 ns 内输出未确定内部信号也没有显示在波形上

我试图展示一个简单的“与”或“反相”电路的仿真结果。一段时间以来，我一直在努力弄清楚这件事的真相。尽管模拟未显示我预期的结果，但代码编译正确。输出信号在 5ns 内显示为未定义，然后显示正确的信号，而我设计中所述的内部信号在仿真期间根本没有显示。

谁能帮我检查我的代码？谢谢。

设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity AOI is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           D : in STD_LOGIC;
           F : out STD_LOGIC);
end AOI;

architecture V1 of AOI is
begin

    F <= (A and B) nor (C and D);

end V1;

architecture V3 of AOI is
    signal I1,I2,I3 : std_logic;  
begin

    F <= not I3 after 1 ns;
    I3 <= I1 or I2 after 2 ns;
    I1 <= A and B after 2 ns;
    I2 <= C and D after 2 ns;
    
end V3;

测试平台

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity andorinvertTB is
end;

architecture TB1 of andorinvertTB is
  
    component AOI_component
        port(A,B,C,D : in std_logic;
             F       : out std_logic);
    end component;
    
       signal A,D,F : std_logic;
    
    for G1: AOI_component use entity work.AOI(V3);

begin

    stimuli: process
    begin
        A <= '0'; B <= '0'; C <= '0'; D <= '0'; wait for 10 NS;
        A <= '0'; B <= '1'; C <= '0'; D <= '1'; wait for 10 NS;
        A <= '1'; B <= '0'; C <= '1'; D <= '0'; wait for 10 NS;
        A <= '1'; B <= '1'; C <= '1'; D <= '1'; wait for 10 NS;
        wait;
    end process;
    
    G1: AOI_component port map ( A=>A,B=>B,C=>C,D=>D,F=>F );
    
end;

Image of simulation results - Output F undefined at the start and missing internal singals I1,I2 and I3