如何解决FIFO Generator 13.2 仿真带 AXI 流接口
你好,我需要你的帮助!
我只想模拟 FIFO Generator 13.2(使用 AXI-Stream)。 当我模拟这个 IP-Core 时,模拟无法正常工作。
如何在不连接任何地方的情况下模拟这个 IP 核。我有一个作业,请帮助我
你可以看到测试台,我需要你帮忙做这个作业。
library ieee;
use ieee.std_logic_1164.all;
entity tb_fifo_axi is
end tb_fifo_axi;
architecture tb of tb_fifo_axi is
component fifo_axi
port (wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector (7 downto 0);
s_axis_tuser : in std_logic_vector (3 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector (7 downto 0);
m_axis_tuser : out std_logic_vector (3 downto 0));
end component;
signal wr_rst_busy : std_logic;
signal rd_rst_busy : std_logic;
signal s_aclk : std_logic;
signal s_aresetn : std_logic;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector (7 downto 0);
signal s_axis_tuser : std_logic_vector (3 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tdata : std_logic_vector (7 downto 0);
signal m_axis_tuser : std_logic_vector (3 downto 0);
constant clk_period : time := 50 ns;
begin
dut : fifo_axi
port map (wr_rst_busy => wr_rst_busy,rd_rst_busy => rd_rst_busy,s_aclk => s_aclk,s_aresetn => s_aresetn,s_axis_tvalid => s_axis_tvalid,s_axis_tready => s_axis_tready,s_axis_tdata => s_axis_tdata,s_axis_tuser => s_axis_tuser,m_axis_tvalid => m_axis_tvalid,m_axis_tready => m_axis_tready,m_axis_tdata => m_axis_tdata,m_axis_tuser => m_axis_tuser);
clk_process :process
begin
s_aclk <= '0';
wait for clk_period/2;
s_aclk <= '1';
wait for clk_period/2;
end process;
stimuli : process
begin
s_axis_tvalid <= '0';
s_axis_tready <= '0';
s_axis_tuser <= (others => '0');
m_axis_tready <= '0';
m_axis_tvalid <= '0';
s_aresetn <= '0';
wait for 20 ns;
s_axis_tdata <= "01010101";
s_axis_tvalid <= '1';
s_axis_tready <= '1';
s_aresetn <= '1';
m_axis_tready <= '1';
m_axis_tvalid <= '1';
wait for 20 ns;
m_axis_tdata <=s_axis_tdata;
wait;
end process;
end tb;
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