如何将 Fifo Generator (13.2) 与 AXI Stream 接口

如何解决如何将 Fifo Generator (13.2) 与 AXI Stream 接口

我需要帮助解决简单的问题。

对于我的学校项目，我需要模拟 FIFO Generator IP 核 (13.2)。但我必须使用 AXI Stream Interface 类型进行模拟。

当我使用实例化模板并编写简单的测试平台时，我收到了“[VRFC 10-3429] 'fifo_axi_default(behavioral)'的非法递归实例化 - 第 49 行”错误。

我不知道如何解决这个问题。你能帮我吗？

我的 VHDL 代码；

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fifo_axi is
port (
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tuser : in std_logic_vector(3 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tuser : out std_logic_vector(3 downto 0)
);
 end fifo_axi;

architecture Behavioral of fifo_axi is
component fifo_axi
port (
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tuser : in std_logic_vector(3 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tuser : out std_logic_vector(3 downto 0)
);
end component;

begin
your_instance_name : fifo_axi
port map (
wr_rst_busy => wr_rst_busy,rd_rst_busy => rd_rst_busy,s_aclk => s_aclk,s_aresetn => s_aresetn,s_axis_tvalid => s_axis_tvalid,s_axis_tready => s_axis_tready,s_axis_tdata => s_axis_tdata,s_axis_tuser => s_axis_tuser,m_axis_tvalid => m_axis_tvalid,m_axis_tready => m_axis_tready,m_axis_tdata => m_axis_tdata,m_axis_tuser => m_axis_tuser
);
end Behavioral;

还有我的测试平台代码；

library ieee;
use ieee.std_logic_1164.all;

entity fifo_axi_tb is
end fifo_axi_tb;

architecture tb of fifo_axi_tb is

component fifo_axi
    port (wr_rst_busy   : out std_logic;
          rd_rst_busy   : out std_logic;
          s_aclk        : in std_logic;
          s_aresetn     : in std_logic;
          s_axis_tvalid : in std_logic;
          s_axis_tready : out std_logic;
          s_axis_tdata  : in std_logic_vector (7 downto 0);
          s_axis_tuser  : in std_logic_vector (3 downto 0);
          m_axis_tvalid : out std_logic;
          m_axis_tready : in std_logic;
          m_axis_tdata  : out std_logic_vector (7 downto 0);
          m_axis_tuser  : out std_logic_vector (3 downto 0));
end component;

signal wr_rst_busy   : std_logic;
signal rd_rst_busy   : std_logic;
signal s_aclk        : std_logic;
signal s_aresetn     : std_logic;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata  : std_logic_vector (7 downto 0);
signal s_axis_tuser  : std_logic_vector (3 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tdata  : std_logic_vector (7 downto 0);
signal m_axis_tuser  : std_logic_vector (3 downto 0);

constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';

begin

dut : fifo_axi
port map (wr_rst_busy   => wr_rst_busy,rd_rst_busy   => rd_rst_busy,s_aclk        => s_aclk,s_aresetn     => s_aresetn,s_axis_tdata  => s_axis_tdata,s_axis_tuser  => s_axis_tuser,m_axis_tdata  => m_axis_tdata,m_axis_tuser  => m_axis_tuser);

-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

-- EDIT: Check that s_aclk is really your main clock signal
s_aclk <= TbClock;

stimuli : process
begin
    -- EDIT Adapt initialization as needed
    s_axis_tvalid <= '0';
    s_axis_tdata <= (others => '0');
    s_axis_tuser <= (others => '0');
    m_axis_tready <= '0';

    -- Reset generation
    -- EDIT: Check that s_aresetn is really your reset signal
    s_aresetn <= '1';
    wait for 100 ns;
    s_aresetn <= '0';
    wait for 100 ns;

    -- EDIT Add stimuli here
    wait for 100 * TbPeriod;

    -- Stop the clock and hence terminate the simulation
    TbSimEnded <= '1';
    wait;
end process;

end tb;

你能帮我吗？