多路复用器不模拟变化

如何解决多路复用器不模拟变化

我对 FPGA 还很陌生，目前我正在尝试实现 MUX。

目前我的代码看起来像这样

entity mux4x1 is
    Port ( S : in std_logic_vector(1 downto 0);
           E : in std_logic_vector(3 downto 0);
           Y : out std_logic);
end mux4x1;

architecture Behavioral of mux4x1 is
signal outputBuff: std_logic;
begin
        Y <= outputBuff; 
        with S select
        outputBuff <=   E(0) when "00",E(1) when "01",E(2) when "10",E(3) when "11",'0' when others;
                              
end Behavioral;

不幸的是，每次我尝试模拟代码并更改输入“S”的值时，E 的值都没有改变！

当我尝试创建比特流时，它显示以下错误报告：

Vivado Commands
General Messages
[USF-XSim-62] 'elaborate' step Failed with error(s). Please check the Tcl console output or 'C:/Users/John Bryan Valle/Documents/Vivado/Programme/Artix-7/MUX4X1/MUX4X1.sim/sim_1/behav/xsim/elaborate.log' file for more information.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

Synthesis
[Designutils 20-970] Unrecognized or unsupported command 'set_property IOSTANDARD LVCMOS33 [get_ports {E[2]}}]' found in constraint file. ["C:/Users/John Bryan Valle/Documents/Vivado/Programme/Artix-7/Lab-1/Lab 1 Full Adder/BASYS 3/Full_Adder_2.xdc":55]

Implementation
Design Initialization
[Designutils 20-970] Unrecognized or unsupported command 'set_property IOSTANDARD LVCMOS33 [get_ports {E[2]}}]' found in constraint file. ["C:/Users/John Bryan Valle/Documents/Vivado/Programme/Artix-7/Lab-1/Lab 1 Full Adder/BASYS 3/Full_Adder_2.xdc":55]

Place Design
DRC
Pin Planning
IO Standard
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 14. For example,the following two ports in this bank have conflicting VCCOs:  
E[2] (LVCMOS18,requiring VCCO=1.800) and E[0] (LVCMOS33,requiring VCCO=3.300)

[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

先谢谢你！ :)

enter image description here

解决方法

E 是一个输入，因此您不会期望它在模拟中自行改变 - 相反，E 和 S 的变化会影响 Y。

当您的数据类型不是 bit 类型时，您应该使用它的库。您使用了 std_logic_vector 数据类型。所以你需要调用它的实现库。该库名为 std_logic_1164。另外，不需要定义中间缓冲区，但它的存在不是问题

library IEEE;
use IEEE.std_logic_1164.all

entity mux4x1 is
  Port ( S : in  std_logic_vector(1 downto 0);
         E : in  std_logic_vector(3 downto 0);
         Y : out std_logic);
end mux4x1;

architecture Behavioral of mux4x1 is
begin
    with S select
    Y <=   E(0) when "00",E(1) when "01",E(2) when "10",E(3) when "11",'0'  when others;
                              
end Behavioral;