如何解决Verilog $ fdisplay不会打印其内容
我设计了AHB兼容SRAM的代码,并设计了测试平台来测试其写入操作。我成功实现了预期的输出。但是,当我打开文件时,“ out.txt”中没有任何内容。我可以看到有效值包含在模拟输出波形的存储变量中,但是现在文本表为空白。我怎样才能解决这个问题?这是我的代码如下:
`timescale 1ns / 1ps
module sram(addr,clk,din,dout,we);
parameter addr_width = 4,word_depth = 16,word_width = 8;
input [addr_width-1:0] addr;
input [word_width-1:0] din;
output [word_width-1:0] dout;
input clk,we;
reg [word_width-1:0] mem [0:word_depth-1];
reg [word_width-1:0] dout;
always @(posedge clk) begin
if(!we)
mem[addr] <= din[word_width-1:0]; //write
end
always @(posedge clk) begin
dout <= mem[addr]; //read
end
endmodule
`timescale 1ns / 1ps
module controller(HCLK,HWRITE,HADDR,HWDATA,HTRANS);
input HCLK,HWRITE;
input [3:0] HADDR;
input [7:0] HWDATA;
input [1:0] HTRANS;
reg HREADY;
reg [3:0] addr;
reg [7:0] din;
reg we;
wire [7:0] dout;
sram sram(addr,we);
assign clk = HCLK;
always @ (posedge HCLK) begin
if(HTRANS==2'b00) begin
addr[3:0] <= HADDR[3:0];
din[7:0] <= HWDATA[7:0];
we <= 0;
HREADY <= 1;
end
end
endmodule
`timescale 1ns / 1ps
module master();
reg HCLK,HWRITE;
reg [3:0] HADDR;
reg [7:0] HWDATA;
reg [1:0] HTRANS;
reg [7:0]in[0:15];
integer sram_pointer;
integer n;
controller controller(HCLK,HTRANS);
always #5 HCLK = ~HCLK;
initial begin
$readmemb("in.txt",master.in);
sram_pointer = $fopen("out.txt");
HCLK = 1;
#2 HWRITE = 1;
for(n = 0; n < 16; n = n + 1) begin
HADDR = n; HTRANS = 2'b10;
#10 HWDATA = in[n]; HTRANS = 2'b00;
#20;
end
#10 for(n = 0; n < 16; n = n + 1) begin
$fdisplay(sram_pointer,"%b",master.controller.sram.mem[n[3:0]]);
end
#30 $finish;
end
endmodule
我尝试将mem[n[3:0]]
转换为mem[n]
,但是没有用。当我转向integer n
时;进入reg [3:0]n;
时,出现了“ for”语句永远循环的问题。
++我试图通过writememb写入数据,所以增加了这句话
$writememb("out.txt",master.controller.sram.mem);
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