如何在测试台VHDL中使用for循环进行多个输入组合？

如何解决如何在测试台VHDL中使用for循环进行多个输入组合？

我是VHDL的新手，我正在为XNOR门编写测试平台。一种简单的解决方案是手动检查两个输入的每个组合，但是输入更多将花费很长时间。如何在VHDL中将其写为for循环？

process
begin
p0 <= '1';
p1 <= '0';
wait for 1 ns;
if (pout = '1') then
    error <= '1';
end if;
wait for 200 ns;
p0 <= '1';
p1 <= '1';
wait for 1 ns;
if (pout = '0') then
    error <= '1';
end if;
wait for 200 ns;
p0 <= '0';
p1 <= '1';
wait for 1 ns;
if (pout = '1') then
    error <= '1';
end if;
wait for 200 ns;
p0 <= '0';
p1 <= '0';
wait for 1 ns;
if (pout = '0') then
    error <= '1';
end if;
wait for 200 ns;
end process;

解决方法

如果p0和p1是被测设备的输入，并且它们的基本类型与类型unsigned的元素类型兼容：

library ieee;
use ieee.std_logic_1164.all;

entity xnor2 is
    port (
        p0:     in  std_logic;
        p1:     in  std_logic;
        pout:   out std_logic
    );
end entity;

architecture foo of xnor2 is
begin
    pout <= not (p0 xor p1);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity inputs is
end entity;

architecture foo of inputs is
    signal p0,p1,pout:    std_logic;
    signal error:           std_logic := '0';
begin
DUT:
    entity work.xnor2
        port map (
            p0 => p0,p1 => p1,pout => pout
        );

    process
        use ieee.numeric_std.all;  -- for example,if not already visible
        variable elements: unsigned (1 downto 0);
    begin
        elements := (others => '0');
        for i in 0 to 2 ** elements'length  - 1 loop
            
            p0 <= elements(0);
            p1 <= elements(1);
            wait for 1 ns;
            report LF & "i = " & integer'image(i) &
                LF & HT & "p0 = " & std_ulogic'image(p0) & 
                         " p1 = " & std_ulogic'image(p1) &
                         " error = " & std_ulogic'image(error);
            if pout = '0' then
                error <= '1';
            end if;
            wait for 200 ns;
            elements := elements + 1;
        end loop;
        wait;
    end process;
end architecture;

哪些报告：

ghdl -r inputs
inputs.vhdl:45:13:@1ns:(report note):
i = 0
    p0 = '0' p1 = '0' error = '0'
inputs.vhdl:45:13:@202ns:(report note):
i = 1
    p0 = '1' p1 = '0' error = '0'
inputs.vhdl:45:13:@403ns:(report note):
i = 2
    p0 = '0' p1 = '1' error = '1'
inputs.vhdl:45:13:@604ns:(report note):
i = 3
    p0 = '1' p1 = '1' error = '1'

我们还看到error没有明显的意义。

如果没有在问题中提供最小，完整和可验证的示例，则答案可能存在一个风险，即可能存在一个或多个错误，以后的读者将无法轻松地验证解决方案。

这里的想法是使用一个二进制表示计数器，该计数器具有与输入一样多的位（元素），并在每次循环迭代中将位（元素）的值分配给相应的输入。

该二进制值也可以直接从loop参数的整数值提供。请参阅How to easily group and drive signals in VHDL testbench，该指南也使用汇总分配：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity agg_assign is
end entity;

architecture foo of agg_assign is
    signal A,B,C: std_logic;
begin
    process
    begin
        wait for 10 ns;
        for i in 0 to 7 loop
            (A,C) <= std_logic_vector(to_unsigned(i,3));
            wait for 10 ns;
        end loop;
        wait;
    end process;
end architecture;

您还可以创建一个记录子类型来混合元素和数组分配：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity aggr_rec_assign is
end entity;

architecture foo of aggr_rec_assign is
    signal A,C: std_logic;
    signal D:       std_logic_vector (2 downto 0);
    
    function to_string (inp: std_logic_vector) return string is
        variable image_str: string (1 to inp'length);
        alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
        end loop;
        return image_str;
    end function;
begin
    process
        type inputs_rec is
        record
                A:  std_logic;
                B:  std_logic;
                C:  std_logic;
                D:  std_logic_vector (2 downto 0);
            end record;
            variable elements:  unsigned (5 downto 0);
    begin
        wait for 10 ns;
        for i in 0 to 2 ** elements'length - 1 loop
            elements := to_unsigned(i,elements'length);
            (A,C,D) <= 
                inputs_rec'(
                    elements(5),elements(4),elements(3),std_logic_vector(elements(2 downto 0))
                );
            wait for 10 ns;
            report LF & HT & "i =  "& integer'image(i) & " (A,D) = " & 
                std_ulogic'image(A) & " " &
                std_ulogic'image(B) & " " &
                std_ulogic'image(C) & " " &
                to_string(D);
        end loop;
        wait;
    end process;
end architecture;

在两种情况下，总分配都是选择从二进制值中提取订单输入的地方。