Nandflash驱动移植系列文章导航：
一共六篇
在飞凌提供的BSP中，Nandflash采用的是FMD+PDD的结构，PDD主要是应对上层的接口，这里我们不需要修改，直接修改FMD就好。（至于在网上看到很多人说这个结构理论上不支持MLC的Nandflash，这个暂且不说）.
FMD部分的驱动源码在 C:\WINCE600\PLATFORM\SMDK6410\src\common\nandflash\FMD\ 这个目录下边。
FMD的目录结构：
nand.s
cfnand.h
fmd_LB.h（实际并没用到）
fmd_SB.h（实际并没用到）
nand.h
fmd.cpp
sources
makefile
先看sources文件：
!if 0 copyright (c) Microsoft Corporation. All rights reserved. !endif !if 0 Use of this sample source code is subject to the terms of the Microsoft license agreement under which you licensed this sample source code. If you did not accept the terms of the license agreement,you are not authorized to use this sample source code. For the terms of the license,please see the license agreement between you and Microsoft or,if applicable,see the LICENSE.RTF on your install media or the root of your tools installation. THE SAMPLE SOURCE CODE IS PROVIDED "AS IS",WITH NO WARRANTIES. !endif !IF 0 Module Name: sources. Abstract: This file specifies the target component being built and the list of sources files needed to build that component. Also specifies optional compiler switches and libraries that are unique for the component being built. !ENDIF TARGETNAME=nandflash_lib11 targettype=LIBRARY RELEASETYPE=PLATFORM SYNCHRONIZE_BLOCK=1 WINCEOEM=1 WINCEcpu=1 NOMIPS16CODE=1 ADEFInes=-pd "_TGTcpu SETS \"$(_TGTcpu)\"" $(ADEFInes) LDEFInes=-subsystem:native /DEBUG /DEBUGTYPE:CV /FIXED:NO INCLUDES=$(INCLUDES) SOURCES=\ fmd.cpp ARM_SOURCES=\ nand.s
这个代码是飞凌提供的，且看这一句 TARGETNAME=nandflash_lib11，经查实，FMD+PDD使用的是FMD产生的nandflash_lib.lib库文件，而不是nandflash_lib11.lib文件，这也说明飞凌在这方面留了一手，并没有直接提供可用的源码，而是给了一个lib库给我们。
在这里，我们需要把 TARGETNAME=nandflash_lib11 修改为 TARGETNAME=nandflash_lib
cfnand.h文件：
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ THIS CODE AND informatION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND,EITHER EXpressed OR IMPLIED,INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR fitness FOR A PARTIculaR PURPOSE. copyright (c) 2001 Microsoft Corporation Module Name: S3C6410.H Abstract: FLASH Media Driver Interface Samsung S3C6410 cpu with NAND Flash controller. Environment: As noted,this media driver works on behalf of the FAL to directly access the underlying FLASH hardware. Consquently,this module needs to be linked with FLASHFAL.LIB to produce the device driver named FLASHDRV.DLL. -----------------------------------------------------------------------------*/ #ifndef _S3C6410_CFNAND_H #define _S3C6410_CFNAND_H #include "FMD_LB.h" #include "FMD_SB.h" #include "nand.h" #define BW_X08 (0) #define BW_X16 (1) #define BW_X32 (2) #define MAX_SECTORS_PER_PAGE (8) /*****************************************************************************/ /* S3C6410 Nand Flash Internal Data Structure DeFinition */ /*****************************************************************************/ typedef struct { UINT16 nMID; /* Manufacturer ID */ UINT16 nDID; /* Device ID */ UINT16 nNumOfBlks; /* Number of Blocks */ UINT16 nPgsPerBlk; /* Number of Pages per block */ UINT16 nSctsPerPg; /* Number of Sectors per page */ UINT16 nNumOfPlanes; /* Number of Planes */ UINT16 nBlksInRsv; /* The Number of Blocks in Reservior for Bad Blocks */ UINT8 nBadPos; /* BadBlock information Poisition*/ UINT8 nLsnPos; /* LSN Position */ UINT8 nECCPos; /* ECC Policy : HW_ECC,SW_ECC */ UINT16 nBWidth; /* Nand Organization X8 or X16 */ UINT16 nTrTime; /* Typical Read Op Time */ UINT16 nTwTime; /* Typical Write Op Time */ UINT16 nTeTime; /* Typical Erase Op Time */ UINT16 nTfTime; /* Typical Transfer Op Time */ } FlashDevSpec; static FlashDevSpec astNandSpec[] = { /*************************************************************************/ /* nMID,nDID,*/ /* nNumOfBlks */ /* nPgsPerBlk */ /* nSctsPerPg */ /* nNumOfPlanes */ /* nBlksInRsv */ /* nBadPos */ /* nLsnPos */ /* nECCPos */ /* nBWidth */ /* nTrTime */ /* nTwTime */ /* nTeTime */ /* nTfTime*/ /*************************************************************************/ /* 8Gbit DDP NAND Flash */ //{ 0xEC,0xD3,8192,64,4,2,160,8,BW_X08,50,350,2000,50},{ 0xEC,4096,128,/* 16Gbit DDP NAND Flash */ { 0xEC,0xD5,// 8192 gjl /* 4Gbit DDP NAND Flash */ { 0xEC,0xAC,80,0xDC,//{ 0xEC,0xBC,BW_X16,0xCC,/* 2Gbit NAND Flash */ { 0xEC,0xAA,2048,1,40,0xDA,0xBA,0xCA,/* 2Gbit DDP NAND Flash */ { 0xEC,/*1Gbit NAND Flash */ { 0xEC,0xA1,1024,20,0xF1,0xB1,0xC1,/* 1Gbit NAND Flash */ { 0xEC,0x79,32,120,5,6,0x78,0x74,11,0x72,/* 512Mbit NAND Flash */ { 0xEC,0x76,70,0x36,/* 512Mbit XP Card */ { 0x98,{ 0x98,0x56,0x46,/* 256Mbit NAND Flash */ { 0xEC,0x75,35,0x35,0x55,0x45,/* 128Mbit NAND Flash */ { 0xEC,0x73,0x33,0x53,0x43,{ 0x00,0x00,0} }; #endif _S3C6410_CFNAND_H
且看
/* 16Gbit DDP NAND Flash */
{ 0xEC,50}这里就是使用的2G（16/8 bit=2byte） Nandflash K9GAG08U0D的一些参数配置，其中 0xEC,0xD5表示的是Nandflash的ID号，总共有4096个block，每个block有128个page，每个page有8个sector
要支持4G（K9LBG08U0D） 的话，则加上下面的配置：
/* 32Gbit DDP NAND Flash */
{ 0xEC,0xD7,
在看nand.h文件之前，我们先来看一下fmd.cpp中引用的#include "s3c6410_nand.h"头文件：（该文件在C:\WINCE600\PLATFORM\COMMON\SRC\SOC\S3C6410_SEC_V1\OAL\INC\s3c6410_nand.h）
// // copyright (c) Microsoft Corporation. All rights reserved. // // // Use of this source code is subject to the terms of the Microsoft end-user // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. // If you did not accept the terms of the EULA,you are not authorized to use // this source code. For a copy of the EULA,please see the LICENSE.RTF on your // install media. // //------------------------------------------------------------------------------ // // Header: s3c6410_nand.h // // Defines the NAND controller cpu register layout and deFinitions. // #ifndef __S3C6410_NAND_H #define __S3C6410_NAND_H #if __cplusplus extern "C" { #endif //------------------------------------------------------------------------------ // Type: S3C6410_NAND_REG // // NAND Flash controller register layout. This register bank is located // by the constant cpu_BASE_REG_XX_NAND in the configuration file // cpu_base_reg_cfg.h. // typedef struct { UINT32 NFCONF; //0x00 // configuration reg UINT32 NFCONT; //0x04 UINT8 NFCMD; //0x08 // command set reg UINT8 d0[3]; UINT8 NFADDR; //0x0C // address set reg UINT8 d1[3]; UINT8 NFDATA; //0x10 // data reg UINT8 d2[3]; UINT32 NFMECCD0; //0x14 UINT32 NFMECCD1; //0x18 UINT32 NFSECCD; //0x1C UINT32 NFSBLK; //0x20 UINT32 NFEBLK; //0x24 // error correction code 2 UINT32 NFSTAT; //0x28 // operation status reg UINT32 NFECCERR0; //0x2C UINT32 NFECCERR1; //0x30 UINT32 NFMECC0; //0x34 // error correction code 0 UINT32 NFMECC1; //0x38 // error correction code 1 UINT32 NFSECC; //0x3C UINT32 NFMLCBITPT; //0x40 } S3C6410_NAND_REG,*ps3C6410_NAND_REG; #if __cplusplus } #endif #endif
注意到了麽？这个跟文档中的寄存器少了8bit ECC寄存器部分。
晕菜了吧，飞凌的这个2G 256M的BSP的Nandflash源码既然是这个样子，为什么还在那里号称8bit的ECC，还说开放源码。
靠别人都行的话，母猪都会上树啦！咱还是自己搞吧！
在上面UINT32 NFMLCBITPT; //0x40 的后面添加以下代码：
UINT32 NF8ECCERR0; //0x44-- 8位ECC错误状态0寄存器 UINT32 NF8ECCERR1; //0x48-- 8位ECC错误状态1寄存器 UINT32 NF8ECCERR2; //0x4c-- 8位ECC错误状态2寄存器 UINT32 NFM8ECC0; //0x50-- 生成8位ECC状态0寄存器 UINT32 NFM8ECC1; //0x54-- 生成8位ECC状态1寄存器 UINT32 NFM8ECC2; //0x58-- 生成8位ECC状态2寄存器 UINT32 NFM8ECC3; //0x5c-- 生成8位ECC状态3寄存器 UINT32 NFMLC8BITPT0; //0x60-- 8位ECC错误位模式寄存器0 UINT32 NFMLC8BITPT1; //0x64-- 8位ECC错误位模式寄存器1
nand.h文件：
// // copyright (c) Microsoft Corporation. All rights reserved. // // // Use of this sample source code is subject to the terms of the Microsoft // license agreement under which you licensed this sample source code. If // you did not accept the terms of the license agreement,you are not // authorized to use this sample source code. For the terms of the license,// please see the license agreement between you and Microsoft or,// see the LICENSE.RTF on your install media or the root of your tools installation. // THE SAMPLE SOURCE CODE IS PROVIDED "AS IS",WITH NO WARRANTIES. // #ifndef __NAND_H__ #define __NAND_H__ //----------------------------------------------------------------------------- typedef struct { UINT16 nNumOfBlks; UINT16 nPagesPerBlk; UINT16 nSctsPerPage; } NANDDeviceInfo; NANDDeviceInfo stDeviceInfo; #ifdef __cplusplus extern "C" { #endif NANDDeviceInfo GetNandInfo(void); #ifdef __cplusplus } #endif #define NUM_OF_BLOCKS (stDeviceInfo.nNumOfBlks) #define PAGES_PER_BLOCK (stDeviceInfo.nPagesPerBlk) #define SECTORS_PER_PAGE (stDeviceInfo.nSctsPerPage) #undef SECTOR_SIZE #define SECTOR_SIZE (512) #define NAND_SECTOR_SIZE (SECTOR_SIZE*SECTORS_PER_PAGE) #define NAND_PAGE_SIZE (SECTOR_SIZE*SECTORS_PER_PAGE) //< Physical Page Size #define IS_LB ((SECTORS_PER_PAGE == 4)||(SECTORS_PER_PAGE == 8)) //----------------------------------------------------------------------------- #define USE_NFCE (0) #define USE_GPIO (0) #define TACLS (NAND_TACLS) #define TWRPH0 (NAND_TWRPH0) #define TWRPH1 (NAND_TWRPH1) #define ECCType (23) //----------------------------------------------------------------------------- #define CMD_READID (0x90) // ReadID #define CMD_READ (0x00) // Read #define CMD_READ2 (0x50) // Read2 #define CMD_READ3 (0x30) // Read3 #define CMD_RESET (0xff) // Reset #define CMD_ERASE (0x60) // Erase phase 1 #define CMD_ERASE2 (0xd0) // Erase phase 2 #define CMD_WRITE (0x80) // Write phase 1 #define CMD_WRITE2 (0x10) // Write phase 2 #define CMD_STATUS (0x70) // STATUS #define CMD_RDI (0x85) // Random Data Input #define CMD_RDO (0x05) // Random Data Output #define CMD_RDO2 (0xE0) // Random Data Output #define BADBLOCKMARK (0x00) // Status bit pattern #define STATUS_READY (0x40) // Ready #define STATUS_ERROR (0x01) // Error #define STATUS_ILLACC (0x20) // Illigar Access #define NF_ECCERR0_ALL_FF 0x40000000 #define NF_ECCERR0_ECC_READY 0x20000000 //----------------------------------------------------------------------------- #define NF_CMD(cmd) {g_pNFConReg->NFCMD = (unsigned char)(cmd);} #define NF_ADDR(addr) {g_pNFConReg->NFADDR = (unsigned char)(addr);} #define NF_nFCE_L() {g_pNFConReg->NFCONT &= ~(1<<1);} #define NF_nFCE_H() {g_pNFConReg->NFCONT |= (1<<1);} #define NF_ECC_DIRECTION_IN() {g_pNFConReg->NFCONT &= ~(1<<18);} #define NF_ECC_DIRECTION_OUT() {g_pNFConReg->NFCONT |= (1<<18);} #define NF_ECC_8BIT_STOP() {g_pNFConReg->NFCONT |= (1<<12);} //stop the last encode or decode of 8bit mode. #define NF_RSTECC() {g_pNFConReg->NFCONT |= ((1<<5) | (1<<4));} #define NF_MSGLENGTH_512() {g_pNFConReg->NFCONF &= ~(1<<25);} #define NF_MSGLENGTH_24() {g_pNFConReg->NFCONF |= (1<<25);} #define NF_ECCTYPE_CLR (g_pNFConReg->NFCONF &= ~(3<<23)) #define NF_ECCTYPE_1BIT() {NF_ECCTYPE_CLR;} #define NF_ECCTYPE_4BIT() {NF_ECCTYPE_CLR |= (1<<24);} #define NF_ECCTYPE_8BIT() {NF_ECCTYPE_CLR |= (1<<23);} #define NF_MECC_UnLock() {g_pNFConReg->NFCONT &= ~(1<<7);} #define NF_MECC_Lock() {g_pNFConReg->NFCONT |= (1<<7);} #define NF_SECC_UnLock() {g_pNFConReg->NFCONT &= ~(1<<6);} #define NF_SECC_Lock() {g_pNFConReg->NFCONT |= (1<<6);} #define NF_CLEAR_RB() {g_pNFConReg->NFSTAT |= (1<<4);} // Have write '1' to clear this bit. #define NF_DETECT_RB() {while((g_pNFConReg->NFSTAT&0x11)!=0x11);} // RnB_Transdetect & RnB #define NF_WAITRB() {while (!(g_pNFConReg->NFSTAT & (1<<0))) ; } #define NF_RDDATA_BYTE() (g_pNFConReg->NFDATA) #define NF_RDDATA_WORD() (*(UINT32 *)0xb0200010) #define NF_WRDATA_BYTE(data) {g_pNFConReg->NFDATA = (UINT8)(data);} #define NF_WRDATA_WORD(data) {*(UINT32 *)0xb0200010 = (UINT32)(data);} #define NF_RDMECC0() (g_pNFConReg->NFMECC0) #define NF_RDMECC1() (g_pNFConReg->NFMECC1) #define NF_RDSECC() (g_pNFConReg->NFSECC) #define NF_RDM8ECC0() (g_pNFConReg->NFM8ECC0) #define NF_RDM8ECC1() (g_pNFConReg->NFM8ECC1) #define NF_RDM8ECC2() (g_pNFConReg->NFM8ECC2) #define NF_RDM8ECC3() (g_pNFConReg->NFM8ECC3) #define NF_RDMECCD0() (g_pNFConReg->NFMECCD0) #define NF_RDMECCD1() (g_pNFConReg->NFMECCD1) #define NF_RDSECCD() (g_pNFConReg->NFSECCD) #define NF_ECC_ERR0 (g_pNFConReg->NFECCERR0) #define NF_ECC_ERR1 (g_pNFConReg->NFECCERR1) #define NF_ECC8BIT_NUM ((g_pNFConReg->NF8ECCERR0 & (0xf<<25))>>25) #define NF_ECC8LOCATION_BYTE1 (g_pNFConReg->NF8ECCERR0 & (0x3ff)) #define NF_ECC8LOCATION_BYTE2 ((g_pNFConReg->NF8ECCERR0 & (0x3ff<<15))>>15) #define NF_ECC8LOCATION_BYTE3 (g_pNFConReg->NF8ECCERR1 & (0x3ff)) #define NF_ECC8LOCATION_BYTE4 ((g_pNFConReg->NF8ECCERR1 & (0x3ff<<11))>>11) #define NF_ECC8LOCATION_BYTE5 ((g_pNFConReg->NF8ECCERR1 & (0x3ff<<22))>>22) #define NF_ECC8LOCATION_BYTE6 (g_pNFConReg->NF8ECCERR2 & (0x3ff)) #define NF_ECC8LOCATION_BYTE7 ((g_pNFConReg->NF8ECCERR2 & (0x3ff<<11))>>11) #define NF_ECC8LOCATION_BYTE8 ((g_pNFConReg->NF8ECCERR2 & (0x3ff<<22))>>22) #define NF_ECC8LOCATION_BIT(n) (n <= 4)?((g_pNFConReg->NFMLC8BITPT0 & (0xff<<((n-1)*8)))>>((n-1)*8)):((g_pNFConReg->NFMLC8BITPT1 & (0xff<<((n-5)*8)))>>((n-5)*8)) #define NF_ECC4BIT_NUM ((g_pNFConReg->NFECCERR0 & (0x7<<26))>>26) #define NF_ECC4LOCATION_BYTE(n) ((n <= 2)?((g_pNFConReg->NFECCERR0 & (0x3ff<<((n-1)*16)))>>((n-1)*16)):((g_pNFConReg->NFECCERR1 & (0x3ff<<((n-3)*16)))>>((n-3)*16))) #define NF_ECC4LOCATION_BIT(n) ((g_pNFConReg->NFMLCBITPT & (0xff<<((n-1)*8)))>>((n-1)*8)) #define NF_WRMECCD0(data) {g_pNFConReg->NFMECCD0 = (data);} #define NF_WRMECCD1(data) {g_pNFConReg->NFMECCD1 = (data);} #define NF_WRSECCD(data) {g_pNFConReg->NFSECCD = (data);} #define NF_RDSTAT (g_pNFConReg->NFSTAT) //----------------------------------------------------------------------------- typedef enum { ECC_CORRECT_MAIN = 0,// correct Main ECC ECC_CORRECT_SPARE1 = 1,// correct Spare for Sector Info using Main ECC Result Area ECC_CORRECT_SPARE2 = 2,// correct Spare for MECC using Main ECC Result Area ECC_CORRECT_SPARE = 3 // correct Spare using Spare ECC Result Area } ECC_CORRECT_TYPE; //----------------------------------------------------------------------------- #endif // __NAND_H_.
nand.h文件里有8bit ECC的相关定义，不要高兴的太早，这里面是有错滴，不知道是不是飞凌那边故意搞错的，还是本来就不是6410的。
且看定义：
#define NF_ECC_8BIT_STOP() {g_pNFConReg->NFCONT |= (1<<12);} //stop the last encode or decode of 8bit mode.
对比文档看一下这个NFCONT[12]是干什么的
NFCONT[11]这个才是8bitStop，但为什么源码中要定义NFCONT[12]为NF_ECC_8BIT_STOP，这个容易让人产生误解。咱还是改一下吧！
#define NF_ECC_8BIT_STOP() {g_pNFConReg->NFCONT |= (1<<11);}
相关引用的暂时到这里，下一篇将会开始源码分析
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