Nandflash驱动移植系列文章导航：
一共六篇
这里将会介绍一下S3C6410cpu中的NFCON，Nandflash控制寄存器
8.1 OVERVIEW
Recently nor flash memory price has increased and pr ice for SDRAM and a NAND flash memory is moderatly placed.
The 6410 is equipped with an internal SRAM buffer called ‘Steppingstone’.
Generally,the boot code will copy NAND flash content to SDRAM. Using hardware ECC,the NAND flash data
validity will be checked. After the NAND flash content is copied to SDRAM,main program will be executed on SDRAM.
To use NAND Flash,'XSELNAND' pin must be connected to High Level.
8.2 FEATURES
NAND flash controller features include:
1. NAND Flash memory I/F: Support 512Bytes and 2KB Page .
2. Software mode: User can directly access NAND flash memory. for example this feature can be used in read/erase/program NAND flash memory.
3. Interface: 8-bit NAND flash memory interface bus.
4. Hardware ECC generation,detection and indication (Software correction).
硬件产生ECC，软件矫正
5. Support both SLC and MLC NAND flash memory : 1-bit ECC,4-bit and 8-bit ECC for NAND flash.
(Recommend: 1bit ECC for SLC,4bit and 8bit ECC for MLC NAND Flash)
同时支持SLC和MLC的Nandflash：1bit ECC用于SLC Nandflash， 4bit和8bit ECC用于MLC Nandflash
6. SFR I/F: Support Byte/half word/word access to Data and ECC Data register,and Word access to other registers
7. SteppingStone I/F: Support Byte/half word/word access.
8. The Steppingstone 8-KB internal SRAM buffer can be used for another purpose .
其他的这里就不废话了，大家看回文档吧。
其中要注意的地方：
Both 4bit and 8bit ECC modules can be used for only 512 bytes ECC parity code generation.
4bit和8bit的ECC模块同时能够用于产生每读写512字节数据对应的ECC校验值。
4 bit and 8bit ECC modules generate the parity codes for each 512 byte. However,1 bit ECC modules generate
parity code per byte lane separately.
4bit ECC modules generate max 7byte parity codes and 8 bit ECC modules generate 13byte parity codes at each
512/24 bytes.
在每读写512或24字节的数据时，4bit的ECC模块产生最多7个字节的ECC校验码，而8bit的ECC模块产生最多13字节的校验码
下面直接来看8bit ECC的编解码：
8.8.5 8-BIT ECC PROGRAMMING GUIDE (ENCODING)
1. To use 8-bit ECC in software mode,set the Ms gLength to 0(512-byte message length) and set the ECCType
to “01”(enable 8-bit ECC). ECC module generates ECC parit y code for 512-byte write data. In order to start
the ECC module,you have to write ‘1’ on the Init MECC (NFCONT[5]) bit after cleaning the MainEcclock
(NFCONT[7]) bit to ‘0’ (Unlock). MainEcclock (NFCONT[7]) bit controls whether ECC Parity code is
generated or not.
Note. In 8bit ECC,MainEcclock should be cleared before initiating InitMECC.
2. Whenever data is written,the 8bit ECC module generates ECC parity code internally.
3. After you finish writing 512-byte data (not include spare area data),the parity codes are automatically updated
to NF8MECC0,NFMECC1,NF8MECC2,NF8MECC3 regi ster. You have to check encoding done at NFSTAT
register. And set the MainEcclock bit to ‘1’(lock). If you use 512-byte page size NAND flash memory,you
can program these values directly to spare area. However,if you use NAND flash memory more than 512-
byte page,you can’t program immediately. In this case,you have to copy these par ity codes to other memory
like DRAM. After writing all main data,you c an write the copied ECC values to spare area.
The parity codes have self-correctable information include parity code itself.
4. To generate spare area ECC parity code,set the MsgLength to 1(24-byte message length),and set the
ECCType to “01”(enable 8bit ECC). 8bit ECC module generates the ECC parity code for 24-byte data. In
order to initiating the module,you have to write ‘1 ’ on the InitMECC (NFCONT[5]) bit after clearing the
MainEcclock (NFCONT[7]) bit to ‘0’(Unlock).
MainEcclock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
Note. In 8bit ECC,MainEcclock should be cleared before initiating InitMECC.
5. Whenever data is written,the 8bit ECC module generates ECC parity code internally.
6. When you finish writing 24-byte Meta or extra data,the parity codes are automatically updated to
NF8MECC0,NF8MECC3 register. you have to check encoding done at NFSTAT
register. And set the MainEcclock bit to ‘1’(lock) . You can program these parity codes to spare area. The
parity codes have self-correctable information include parity code itself.
部分译文：（仅供参考）
8.8.6 8-BIT ECC PROGRAMMING GUIDE (DECODING)
1. To use 8bit ECC in software mode,set the MsgLength to 0(512-byte message length) and set the ECCType
to “01”(enable 8bit ECC). 8bit ECC module generates E CC parity code for 512-byte read data. In order to
initiating 8bit ECC module,you have to write ‘1’ on the InitMECC (NFCONT[5]) bit after clearing the
MainEcclock (NFCONT[7]) bit to ‘0’(Unlock).
MainEcclock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
Note. In 8bit ECC,MainEcclock should be cleared before InitMECC
2. Whenever data is read,the MLC ECC m odule generates ECC parity code internally.
3. After you complete reading 512-byte data (not including spare area data),you must set the MainEcclock
(NFCONT[7]) bit to ‘1’(Lock) after reading parity codes. 8bit ECC module needs parity codes to detect
whether error bits exists or not. So you have to read the ECC parity code of 512-byte main data right after
reading the 512-byte data. Once the ECC parity code is read,8bit ECC engine starts searching any error
internally. 8bit ECC error searching engine needs mini mum 372 cycles to find any error. And set the
MainEcclock bit to ‘1’(lock). ECCDecDone(NFSTAT[6]) can be used to check whether ECC decoding is
completed or not.
4. When ECCDecDone (NFSTAT[6]) is set (‘1’),NF8ECCERR0 indicates whether error bit exists or not. If any
error exists,you can fix it by referencing NF8ECCERR0/1/2 and NFMLC8BITPT0/1 register.
5. If you have more main data to read,continue doing from step 1.
6. For Meta data error check,set the MsgLength to 1(24-byte message length) and set the ECCType to
“01”(enable 8bit ECC). ECC module generates the ECC parity code for 24-byte data. In order to initiating the
8bit ECC module,you have to write ‘1’ on the InitMECC (NFCONT[5]) bit after clearing the MainEcclock
(NFCONT[7]) bit to ‘0’(Unlock).
MainEcclock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
Note. In 8bit ECC,MainEcclock should be cleared before InitMECC
7. Whenever data is read,the 8bit ECC module generates ECC parity code internally.
8. After you complete reading 24-byte,you must set the MainEcclock (NFCONT[7]) bit to ‘1’(Lock) after read
ing the parity code for 24-byte data. MLC ECC module needs parity codes to detect w hether error bits exists
or not. So you have to read ECC parity codes right after reading 24-byte data. Once ECC parity code is read,
8bit ECC engine starts searching any error internally. 8bit ECC error searching engine needs minimum 372
cycles to find any error. And set the MainEcclock bit to ‘1’(lock). ECCDecDone(NFSTAT[6]) can be used to
check whether ECC decoding is completed or not.
9. When ECCDecDone (NFSTAT[6]) is set (‘1’),NF8ECCERR0 indicates whether error bit exist or not. If any
error exists,you can fix it by referencing NF8ECCERR0/1/2 and NF8MLCBITPT register.
部分译文：（仅供参考）
PS: 原文中有些寄存器是写错的，大家在看的时候要注意。
吐槽一下，三星这个文档实在是简陋的可以，而且错误的地方还很多，想不BS一下都不成。
在这里有个地方要注意的是：
在写数据到Nandflash的时候，每写512字节就会产生一次ECC，我们这里用的是4K页，大于512字节，所以必须把产生的ECC校验值保存起来，等到一页（4k）写完，再把这些ECC写入到备用区中。
而在读取数据的时候，却是每读取512字节的主数据，就会产生一次ECC，这时就要进行ECC校验、矫正了。和写的时候不大一样，需要注意这一点。
寄存器部分：
红色框住是主要使用的寄存器和8bit ECC所用到的寄存器。
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