1. Simple wire
module top_module( input in, output out );
assign out = in ;
endmodule
2. Four wires
module top_module(
input a,b,c,
output w,x,y,z );
assign w=a;
assign x=b;
assign y=b;
assign z=c;
endmodule
3. Inverter
module top_module( input in, output out );
assign out = ~in;
endmodule
4. AND gate
module top_module(
input a,
input b,
output out );
assign out = a&b;
endmodule
5. nor gate
module top_module(
input a,
input b,
output out );
assign out = ~(a|b);
endmodule
6. Xnor gate
module top_module(
input a,
input b,
output out );
assign out = ~(a^b);
endmodule
7. Declaring wires
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n);
wire temp1,temp2;
assign temp1 = a&b;
assign temp2 = c&d;
assign out = temp1 | temp2;
assign out_n = ~out;
endmodule
8. 7458 chip
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = (p1a & p1b & p1c)|(p1d & p1e & p1f);
assign p2y = (p2a & p2b)|(p2c & p2d);
endmodule
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