如何解决模块没有与组件端口“en”匹配的正式端口
我对 vhdl 非常熟悉,我正在 Vivado 中执行此操作。所有这些代码都是自动生成的,我只是添加了端口“framesize”、“en”和“axi_en”,然后将它们映射到组件中。 但是,当我与其他人一起使用该组件时,出现此错误: [Synth 8-3493] 在 'directory/sample_generator_v1_0_S00_AXIS.vhd:5' 中声明的模块 'sample_generator_v1_0_s00_axis' 没有与组件端口 'en' 匹配的正式端口
请帮帮我。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_generator_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXIS
C_S00_AXIS_TDATA_WIDTH : integer := 32;
-- Parameters of Axi Master Bus Interface M00_AXIS
C_M00_AXIS_TDATA_WIDTH : integer := 32;
C_M00_AXIS_START_COUNT : integer := 32
);
port (
-- Users to add ports here
-- User ports ends
framesize : in std_logic_vector(7 downto 0);
en : in std_logic;
axi_en : in std_logic;
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXIS
s00_axis_aclk : in std_logic;
s00_axis_aresetn : in std_logic;
s00_axis_tready : out std_logic;
s00_axis_tdata : in std_logic_vector(C_S00_AXIS_TDATA_WIDTH-1 downto 0);
s00_axis_tstrb : in std_logic_vector((C_S00_AXIS_TDATA_WIDTH/8)-1 downto 0);
s00_axis_tlast : in std_logic;
s00_axis_tvalid : in std_logic;
-- Ports of Axi Master Bus Interface M00_AXIS
m00_axis_aclk : in std_logic;
m00_axis_aresetn : in std_logic;
m00_axis_tvalid : out std_logic;
m00_axis_tdata : out std_logic_vector(C_M00_AXIS_TDATA_WIDTH-1 downto 0);
m00_axis_tstrb : out std_logic_vector((C_M00_AXIS_TDATA_WIDTH/8)-1 downto 0);
m00_axis_tlast : out std_logic;
m00_axis_tready : in std_logic
);
end sample_generator_v1_0;
architecture arch_imp of sample_generator_v1_0 is
-- component declaration
component sample_generator_v1_0_S00_AXIS is
generic (
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port (
--START OF USER'S PORT
en : in std_logic;
--END OF USER'S PORT
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic
);
end component sample_generator_v1_0_S00_AXIS;
component sample_generator_v1_0_M00_AXIS is
generic (
C_M_AXIS_TDATA_WIDTH : integer := 32;
C_M_START_COUNT : integer := 32
);
port (
--USER'S PORTS
framesize : in std_logic_vector(7 downto 0);
axi_en : in std_logic;
--ENS USER'S PORTS
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
);
end component sample_generator_v1_0_M00_AXIS;
begin
-- Instantiation of Axi Bus Interface S00_AXIS
sample_generator_v1_0_S00_AXIS_inst : sample_generator_v1_0_S00_AXIS
generic map (
C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TDATA_WIDTH
)
port map (en,s00_axis_aclk,s00_axis_aresetn,s00_axis_tready,s00_axis_tdata,s00_axis_tstrb,s00_axis_tlast,s00_axis_tvalid);
--en map the EN User port
-- Instantiation of Axi Bus Interface M00_AXIS
sample_generator_v1_0_M00_AXIS_inst : sample_generator_v1_0_M00_AXIS
generic map (
C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_TDATA_WIDTH,C_M_START_COUNT => C_M00_AXIS_START_COUNT
)
port map (framesize,axi_en,m00_axis_aclk,m00_axis_aresetn,m00_axis_tvalid,m00_axis_tdata,m00_axis_tstrb,m00_axis_tlast,m00_axis_tready);
-- Add user logic here
-- User logic ends
end arch_imp;```
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