ISIM 显示 U 为时钟

如何解决ISIM 显示 U 为时钟

我试图将 AM 调制信号模拟为 (1+0.2cos(2pi94Hz))sin(2pi430kHz)。 我在 MATLAB Simulink 中模拟了它的定点模型，找到了足够多的二进制点，并将输出打印在文本文件中，以便随后与 ISE Isim 模拟进行比较。当我模拟时，在 Isim 中它显示 U 代表时钟，XX 代表两个信号。我不明白为什么。这是我的代码：

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AM_mod_VHDL is
    Port  ( 
                    Output_Signal : out  signed (10 downto 0);
                    Clock         : in   STD_LOGIC
              );
end AM_mod_VHDL;

architecture Behavioral of AM_mod_VHDL is
        signal   Output_Signal_int :  signed           (10 downto 0):=(others=>'0');
        signal   cosine_DDS        :  std_logic_vector (8 downto 0) :=(others=>'0');
        signal   sine_DDS          :  std_logic_vector (8 downto 0) :=(others=>'0');
        signal   product_cosine02  :  signed           (15 downto 0):=(others=>'0');
        signal   product_final     :  signed           (18 downto 0):=(others=>'0');
        signal   med_output        :  signed           (9 downto 0) :=(others=>'0');
        constant coefficent_02     :  signed           (6 downto 0) :=to_signed(13,7);
        constant coefficent_1      :  signed           (1 downto 0) :="01";

    COMPONENT Cosine_94Hz_IPCore
      PORT (
                 clk    : IN STD_LOGIC;
                 cosine : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
           );
    END COMPONENT;
    
    COMPONENT Cosine_430kHz
    PORT   (
                clk         : IN STD_LOGIC;
                sine       : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
           );
    END COMPONENT;
        
begin
        Output_Signal <= Output_Signal_int;
        
            cosine_94Hz : Cosine_94Hz_IPCore
            PORT MAP (
                            clk    => Clock,cosine => cosine_DDS
                        );  
                        
            sine_430kHz : Cosine_430kHz
           PORT MAP (
                            clk => Clock,sine => sine_DDS
                     );
    process(Clock)
    begin
        if rising_edge(Clock) then
            product_cosine02  <= signed(cosine_DDS)*coefficent_02;
            med_output        <= product_cosine02(15 DOWNTO 6) + coefficent_1;
            product_final     <= med_output*signed(sine_DDS);
            Output_Signal_int <= product_final(18 downto 8);
        end if;
    end process;

end Behavioral;

这是我的测试平台代码：

    LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

use ieee.std_logic_textio.all;
use std.textio.all;
 
ENTITY Simple_Algorithm_VHDL_tb IS
END Simple_Algorithm_VHDL_tb;
 
ARCHITECTURE behavior OF Simple_Algorithm_VHDL_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT AM_mod
    PORT(
         Clock : IN  std_logic;
         Output_Signal : out  signed (10 downto 0);
        );
    END COMPONENT;
    

   --Inputs
   signal Clock : std_logic := '0';

    --Outputs
   signal Output_Signal : signed(10 downto 0);

   -- Clock period definitions
   constant Clock_period : time := 10 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: Top_Module PORT MAP (
          Clock => Clock,Output_Signal => Output_Signal
        );

   -- Clock process definitions
   Clock_process :process
   begin
        Clock <= '0';
        wait for Clock_period/2;
        Clock <= '1';
        wait for Clock_period/2;
   end process;
 
    write_Output_Vector: process(Clock)
    
        file        output_text : text open write_mode is "\Examples\AM_mod\AM_mode_MATLAB\Output_Vec_HDL.txt";
        variable LO1            : line;
        
    begin
    
        if rising_edge(Clock) then
        
            write(LO1,to_integer(Output_Signal));
            writeline(output_text,LO1);
            
        end if;
    end process;

END;

这是 Isim 给我看的：