如何解决未连接的端口-Verilog 综合错误
我正在综合我的 RTL,但我一直收到错误“警告:在设计中‘DasisyChain3’端口‘m1_data[7]’未连接到任何网络 (LINT-28)。我不知道为什么它会告诉我这个。我在我的设计中包含了所有模块,它代表了 SPI 协议的某种简化版本。我有一个从主机和 DaisyChain 模块,它是我的顶级模块,是菊花链的实现。
module DaisyChain3(output [7:0] s1_buff,s2_buff,s3_buff,input EN,CLK,input [7:0] m1_data,s1_data,s2_data,s3_data);
wire SCLK,CS,MOSI;
wire s1_SOMI,s2_SOMI,s3_SOMI;
SPIMaster m1(SCLK,MOSI,EN,s3_SOMI,m1_data);
SPISlave s1(s1_SOMI,s1_buff,SCLK,s1_data);
SPISlave s2(s2_SOMI,s1_SOMI,s2_data);
SPISlave s3(s3_SOMI,s3_data);
endmodule
module SPIMaster(output reg SCLK,MISO,input [7:0] m_data);
wire master_out;
reg [4:0] count,count1,count2;
wire [7:0] data_buff;
wire SCLK1;
reg master_in,c_sw,k,state,load;
reg k1,load1;
shiftReg register_out (master_out,data_buff,load,(~SCLK1),master_in,m_data);
assign SCLK1 = (~c_sw) | CLK;
always@(posedge CLK) begin
if(state) begin
if (k == 1) begin
state <= 0;
c_sw <= 0;
CS <= 1;
count <= 0;
k <= 0;
load <= 0;
end
else begin
state <= 1;
c_sw <= 1;
CS <= 0;
end
end
else begin
if (EN) begin
state <= 1;
c_sw <= 1;
CS <= 0;
count <= 0;
k <= 0;
load <= 1;
end
end
count <= count1;
load <= load1;
k <= k1;
end
always@(posedge SCLK1) begin
load1 <= count;
count1 <= count;
if (CS == 0) master_in <= MISO;
if (count1 == 7) begin
load1 <= 0;
end
else if (count1 == 15)begin
load1 <= 0;
end
else begin
load1 <= 1;
end
count1 <= count2;
end
always@(negedge SCLK1) begin
count2 <= count1;
k1 <= k;
if (count2 == 23) k1 <= 1;
else k1 <= 0;
if (CS == 0) begin
MOSI <= master_out;
count2 <= count2 + 1;
end
end
endmodule
module SPISlave(output reg SOMI,output [7:0] data_buff,input SIMO,input [7:0] s_data);
wire clk;
reg slave_in;
wire slave_out;
shiftReg register_out (slave_out,(~CS),clk,slave_in,s_data);
assign clk = SCLK | CS;
always@(posedge clk) begin
slave_in <= SIMO;
end
always@(negedge clk) begin
SOMI <= slave_out;
end
endmodule
module shiftReg(output shift_out,output reg [7:0] data_buff,input shift_write,shift_in,input [7:0] data);
reg [7:0] buffer;
assign shift_out = buffer[7];
assign buffer[0] = shift_in;
always@(posedge clk) begin
if(shift_write == 1) begin
buffer <= {buffer[6:0],shift_in};
end
end
always@(shift_write) begin
if(shift_write == 0) begin
data_buff <= buffer;
buffer <= data;
end
end
endmodule
解决方法
在您之前的消息中,您忘记发布 shiftReg 的代码。它就在这里,它有一个错误,这可能是造成上一个问题的原因,也可能是这个问题的原因。
您的问题是您有多个 (3) 个用于 buffer 的驱动程序:
assign buffer[0] = shift_in; <<< driver 1
always@(posedge clk) begin
if(shift_write == 1) begin
buffer <= {buffer[6:0],shift_in}; <<< driver 2
end
end
always@(shift_write) begin
if(shift_write == 0) begin
data_buff <= buffer;
buffer <= data; <<< driver 3
end
end
您有触发器、锁存器和组合逻辑驱动相同的信号。您需要确保信号由单个 always 块驱动。目前您有未定义的模拟行为,混淆了合成器和 linter(它也是一个合成器)。
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