如何向输入序列 VHDL 添加奇偶校验位

如何解决如何向输入序列 VHDL 添加奇偶校验位

我正在 VHDL 上为给定的输入位序列 (10100110) 制作 FSM Moore 序列检测器，但现在我还想向输入位序列添加偶校验位作为新序列。我知道使用异或门的逻辑，但我无法在代码中实现它。

这是我的设计代码：

library IEEE;
use IEEE.std_logic_1164.all;

entity sequence_detector is
    port(clock: in std_logic;
        input_seq: in std_logic;
        detector: out std_logic);   
end sequence_detector;

architecture behaviour of sequence_detector is
    type state is (init,s1,s2,s3,s4);
    signal p_s,n_s : state;
    begin

        process
        begin 
            wait until clock'event and clock = '1';
                p_s <= n_s;
        end process;
        
        process (input_seq,p_s)
        begin
       
                case(p_s) is
                  when init =>
                      if(input_seq = '1') then
                          n_s <= s1;
                          detector <= '0';
                      else
                          n_s <= init;
                          detector <= '0';
                      end if;
                  when s1 =>
                      if(input_seq = '0') then
                          n_s <= s2;
                          detector <= '0';
                      else
                          n_s <= s1;
                          detector <= '0';
                      end if;
                  when s2 =>
                      if(input_seq = '0') then
                          n_s <= s3;
                          detector <= '0';
                      else
                          n_s <= s1;
                          detector <= '0';
                      end if;
                  when s3 =>
                      if(input_seq = '1') then
                          n_s <= s4;
                          detector <= '0';
                      else
                          n_s <= init;
                          detector <= '0';
                      end if;
                  when s4 =>      --here we decide if its overlapping or not
                      if(input_seq = '1') then
                          n_s <= s1;
                          detector <= '1';
                      else
                          n_s <= s2;
                          detector <= '0';
                      end if;
              end case;
        end process; 
end behaviour;

这是我的测试平台：

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
end testbench;

architecture behaviour of testbench is
    component sequence_detector is
    port(clock: in std_logic;
        input_seq: in std_logic;
        detector: out std_logic);
    end component;

    signal clock,input_seq : std_logic;
    signal detector : std_logic;

    constant clock_period: Time := 10 ns;
    begin
        DUT: sequence_detector port map(clock,input_seq,detector);
        p_clock: process
        begin
            clock <= '0';
            wait for clock_period/2;
            clock <= '1';
            wait for clock_period/2;
        end process;

        process
        begin
            input_seq <= '1';
            wait for 10 ns;
            input_seq <= '0';
            wait for 10 ns;
            input_seq <= '1';
            wait for 20 ns;
            input_seq <= '0';
            wait for 20 ns;
            input_seq <= '1';
            wait for 20 ns;
            input_seq <= '0';

            wait;
        end process;    
end behaviour;

这是输出： output graph