将 12 个向量加在一起只是在模拟中未定义所有输入和输出

如何解决将 12 个向量加在一起只是在模拟中未定义所有输入和输出

我正在尝试将来自 12 个不同部分 (A-L) 的出席人数相加，以获得总体出席人数。每个部分的输入是一个 9 位向量，所有这些向量相加形成一个 14 位向量。然而，当我尝试实现一个测试平台时，我将所有输入和输出都定义为未定义，并且没有任何波形。任何指导将不胜感激！

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity overall_attendance_data is
  Port (OUTPUTDATA_A    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_B    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_C    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_D    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_E    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_F    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_G    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_H    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_I    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_J    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_K    : in STD_LOGIC_VECTOR(8 downto 0);
        OUTPUTDATA_L    : in STD_LOGIC_VECTOR(8 downto 0);
        OVERALL_ATTENDANCE_DATA_OUT : out STD_LOGIC_VECTOR(13 downto 0));
end overall_attendance_data;

architecture Behavioral of overall_attendance_data is
    signal OVERALL_ATTENDANCE : unsigned(13 downto 0); 
begin
    -- '0' & prevents overflow
    OVERALL_ATTENDANCE <= ('0' & unsigned(OUTPUTDATA_A)) + ('0' & unsigned(OUTPUTDATA_B)) + ('0' & unsigned(OUTPUTDATA_C)) + ('0' & unsigned(OUTPUTDATA_D)) + ('0' & unsigned(OUTPUTDATA_E)) + ('0' & unsigned(OUTPUTDATA_F)) + ('0' & unsigned(OUTPUTDATA_G)) + ('0' & unsigned(OUTPUTDATA_H)) + ('0' & unsigned(OUTPUTDATA_I)) + ('0' & unsigned(OUTPUTDATA_J)) + ('0' & unsigned(OUTPUTDATA_K)) + ('0' & unsigned(OUTPUTDATA_L)); 
    
    OVERALL_ATTENDANCE_DATA_OUT <= std_logic_vector(OVERALL_ATTENDANCE);
end Behavioral;

下面查看测试台，测试所有等于 1 的输入。

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity OVERALL_ATTENDANCE_DATA_tb is
end;

architecture bench of OVERALL_ATTENDANCE_DATA_tb is

  component overall_attendance_data
    Port (OUTPUTDATA_A    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_B    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_C    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_D    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_E    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_F    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_G    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_H    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_I    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_J    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_K    : in STD_LOGIC_VECTOR(8 downto 0);
          OUTPUTDATA_L    : in STD_LOGIC_VECTOR(8 downto 0);
          OVERALL_ATTENDANCE_DATA_OUT : out STD_LOGIC_VECTOR(13 downto 0));
  end component;

  signal OUTPUTDATA_A: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_B: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_C: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_D: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_E: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_F: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_G: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_H: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_I: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_J: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_K: STD_LOGIC_VECTOR(8 downto 0);
  signal OUTPUTDATA_L: STD_LOGIC_VECTOR(8 downto 0);
  signal OVERALL_ATTENDANCE_DATA_OUT: STD_LOGIC_VECTOR(13 downto 0);

begin

  stimulus: process
  begin
    
       OUTPUTDATA_A <= "000000001"; OUTPUTDATA_B <= "000000001"; OUTPUTDATA_C <= "000000001"; OUTPUTDATA_D <= "000000001"; OUTPUTDATA_E <= "000000001"; OUTPUTDATA_F <= "000000001"; OUTPUTDATA_G <= "000000001"; OUTPUTDATA_H <= "000000001"; OUTPUTDATA_I <= "000000001"; OUTPUTDATA_J <= "000000001"; OUTPUTDATA_K <= "000000001"; OUTPUTDATA_L <= "000000001"; wait for 100ns;
  end process;

  dut: overall_attendance_data port map ( OUTPUTDATA_A                => OUTPUTDATA_A,OUTPUTDATA_B                => OUTPUTDATA_B,OUTPUTDATA_C                => OUTPUTDATA_C,OUTPUTDATA_D                => OUTPUTDATA_D,OUTPUTDATA_E                => OUTPUTDATA_E,OUTPUTDATA_F                => OUTPUTDATA_F,OUTPUTDATA_G                => OUTPUTDATA_G,OUTPUTDATA_H                => OUTPUTDATA_H,OUTPUTDATA_I                => OUTPUTDATA_I,OUTPUTDATA_J                => OUTPUTDATA_J,OUTPUTDATA_K                => OUTPUTDATA_K,OUTPUTDATA_L                => OUTPUTDATA_L,OVERALL_ATTENDANCE_DATA_OUT => OVERALL_ATTENDANCE_DATA_OUT );

end;

Simulation results from testbench