存储在变量if语句内部的条件评估给出正确的结果，而直接存储在assert中的评估给出错误的结果

如何解决存储在变量if语句内部的条件评估给出正确的结果，而直接存储在assert中的评估给出错误的结果

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EqTB is
end EqTB;

architecture Behavioral of EqTB is
    signal a_in,b_in: STD_LOGIC_VECTOR(1 DOWNTO 0);
    signal y_in: STD_LOGIC;
    component EqCmp is 
        port(
            a,b: in STD_LOGIC_VECTOR(1 DOWNTO 0);
            y: out STD_LOGIC
        );
    end component;
begin
    DUT: EqCmp port map(a => a_in,b => b_in,y => y_in);
    process
    begin
        a_in <= b"00";
        b_in <= b"01";
        wait for 100 ns;
        a_in <= b"11";
        b_in <= b"11";
        wait for 100 ns;
        a_in <= b"00";
        b_in <= b"00";
        wait for 100 ns;
        a_in <= b"11";
        b_in <= b"00";
        wait for 100 ns;
    end process;
    
    process (all)
        variable EQ: BOOLEAN := false;
    begin
--        if (((a_in = b_in) = true)  and y_in ='1')
--        or (((a_in = b_in) = false) and y_in = '0') then
--            EQ := true;
--        end if;
        EQ := (((a_in = b_in) = true)  and y_in ='1')
           or (((a_in = b_in) = false) and y_in = '0');
        assert (EQ)
            report "Fault occurred. " & std_logic'image(y_in) & boolean'image(EQ)
            severity ERROR;
    end process;
end Behavioral;

前面的代码是下面模块的Testbench：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity EqCmp is
    Port(
        a: in STD_LOGIC_VECTOR(1 DOWNTO 0);
        b: in STD_LOGIC_VECTOR(1 DOWNTO 0);
        y: out STD_LOGIC
    );
end EqCmp;

architecture Behavioral of EqCmp is    
begin
    y <= '1' when (a = b) else '0';    
end Behavioral;

问题出在测试台上，最后一个process中的注释代码工作正常，但是当我直接在流程的外部主体中分配EQ而不使用if语句时，它给出了以下报告。

Error: Fault occurred. 'U' false
Time: 0 ps  Iteration: 0  Process: /EqTB/line__34 
Error: Fault occurred. '1' false
Time: 0 ps  Iteration: 1  Process: /EqTB/line__34  
Error: Fault occurred. '0' false
Time: 100 ns  Iteration: 1  Process: /EqTB/line__34
Error: Fault occurred. '1' false
Time: 300 ns  Iteration: 1  Process: /EqTB/line__34
Error: Fault occurred. '0' false
Time: 500 ns  Iteration: 1  Process: /EqTB/line__34
Error: Fault occurred. '1' false
Time: 700 ns  Iteration: 1  Process: /EqTB/line__34
Error: Fault occurred. '0' false
Time: 900 ns  Iteration: 1  Process: /EqTB/line__34

这是模拟结果，似乎是正确的：

我还指出，它仅发生在输出的变化沿。否则，例如，如果输出保持高电平，则不会产生错误。